Many of today's computing devices (e.g., laptop computers, desktop computers, smartphones, tablets, and servers) utilize processors that conform to an instruction set architecture known commercially as the ARM™ (Advanced RISC Machines) architecture. ARM processors may have multiple processing elements located on a single device (e.g., processor). According to the ARM architecture, when a device has multiple processing elements, each processing element must have access to a global system counter (e.g., timer). Such a requirement ensures that all of the processing elements have a consistent notion of time.
In some current systems that have multiple processing elements (e.g., cores) on a single device, each of the processing elements has a dedicated parallel bus that is used to send the global timer value to that particular processing element, and each time the global timer value is updated for the processing elements, the new global timer value is sent again over the dedicated buses. However, such a configuration can cause problems when a large number of processing elements are present on the single device.
Synchronization is even more difficult to achieve in systems that utilize multiple devices, each having multiple processing elements that all must have access to the same global system counter.